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general description the MAX16833/MAX16833bCMAX16833d are peak current-mode-controlled led drivers for boost, buck- boost, sepic, flyback, and high-side buck topologies. a dimming driver designed to drive an external p-channel in series with the led string provides wide-range dim - ming control. this feature provides extremely fast pwm current switching to the leds with no transient overvolt - age or undervoltage conditions. in addition to pwm dim- ming, the ics provide analog dimming using a dc input at ictrl. the ics sense the led current at the high side of the led string. a single resistor from rt/sync to ground sets the switching frequency from 100khz to 1mhz, while an external clock signal capacitively coupled to rt/sync allows the ics to synchronize to an external clock. in the MAX16833/MAX16833c, the switching frequency can be dithered for spread-spectrum applications. the MAX16833b/MAX16833d instead provide a 1.64v refer - ence voltage with a 2% tolerance. the ics operate over a wide 5v to 65v supply range and include a 3a sink/source gate driver for driving a power mosfet in high-power led driver applica - tions. additional features include a fault-indicator output (flt) for short or overtemperature conditions and an overvoltage-protection sense input (ovp) for overvoltage protection. high-side current sensing combined with a p-channel dimming mosfet allow the positive terminal of the led string to be shorted to the positive input termi - nal or to the negative input terminal without any damage. this is a unique feature of the ics. features s boost, sepic, and buck-boost single-channel led drivers s +5v to +65v wide input voltage range with a maximum 65v boost output s integrated high-side current-sense amplifier s ictrl pin for analog dimming s integrated high-side pmos dimming mosfet driver (allows single-wire connection to leds) s programmable operating frequency (100khz to 1mhz) with synchronization capability s frequency dithering for spread-spectrum applications (MAX16833/MAX16833c) s 2% accurate 1.64v reference (MAX16833b/ MAX16833d) s full-scale, high-side, current-sense voltage of 200mv s short-circuit, overvoltage, and thermal protection s fault indicator output s -40nc to +125nc operating temperature range s thermally enhanced 5mm x 4.4mm, 16-pin tssop package with exposed pad 19-5187; rev 6; 8/13 ordering information continued at end of data sheet. applications automotive exterior lighting: high-beam/low-beam/signal/position lights daytime running lights (drls) fog light and adaptive front light assemblies commercial, industrial, and architectural lighting simplified operating circuit ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. /v denotes an automotive qualified part. pwmdim in ndrv cs ovp isense+ isense- pgnd 6v to 18v with load dump up to 70v led+ led- pwmdim dimout MAX16833 part temp range pin-package functionality max duty cycle (%) MAX16833aue+ -40c to +125c 16 tssop-ep* frequency dithering 88.5 MAX16833aue/v+ -40c to +125c 16 tssop-ep* frequency dithering 88.5 MAX16833/MAX16833bCMAX16833d high-voltage hb led drivers with integrated high-side current sense evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in to pgnd ........................................................... -0.3v to +70v isense+, isense-, dimout to pgnd ................ -0.3v to +80v dimout to isense+ ............................................... -9v to +0.3v isense- to isense+ ............................................ -0.6v to +0.3v pgnd to sgnd .................................................... -0.3v to +0.3v v cc to pgnd .......................................................... -0.3v to +9v ndrv to pgnd ........................................ -0.3v to (v cc + 0.3v) ovp, pwmdim, comp, lframp, ref, ictrl, rt/sync, flt to sgnd ................................... -0.3v to +6.0v cs to pgnd ......................................................... -0.3v to +6.0v continuous current on in ................................................ 100ma peak current on ndrv ........................................................ q3a continuous current on ndrv ....................................... q100ma short-circuit duration on v cc ................................... continuous continuous power dissipation (t a = +70n c) 16-pin tssop (derate 26.1mw/ nc above +70nc) ..... 2089mw operating temperature range ...................... -40nc to +125nc junction temperature ..................................................... +150nc storage temperature range ............................ -65nc to +150nc lead temperature (soldering, 10s) ................................ +300nc soldering temperature (reflow) ...................................... +260nc electrical characteristics (v in = 12v, r rt = 12.4ki, c in = c vcc = 1f, c lframp /c ref = 0.1f, ndrv = comp = dimout = pwmdim = flt = unconnected, v ovp = v cs = v pgnd = v sgnd = 0v, v isense+ = v isense- = 45v, v ictrl = 1.40v, t a = t j = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 2) absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. 16 tssop junction-to-ambient thermal resistance ( q ja ) ....... 38.3c/w junction-to-case thermal resistance ( q jc ) ................. 3c/w package thermal characteristics (note 1) parameter symbol conditions min typ max units system specifications operational supply voltage v in 5 65 v supply current i inq pwmdim = 0, no switching 1.5 2.5 ma switching 2.5 4 undervoltage lockout (uvlo) uvlor in v in rising 4.2 4.55 4.85 v uvlof in v in falling, i vcc = 35ma 4.05 4.3 4.65 uvlo hysteresis 250 mv startup delay t start_delay during power-up 410 fs uvlo falling delay t fall_delay during power-down 3.3 fs v cc ldo regulator regulator output voltage v cc 0.1ma p i vcc p 50ma, 9v p v in p 14v 6.75 6.95 7.15 v 14v p v in p 65v, i vcc = 10ma dropout voltage v dovcc i vcc = 50ma, v in = 5v 0.15 0.35 v short-circuit current i maxvcc v cc = 0v, v in = 5v 55 100 150 ma oscillator (rt/sync) switching frequency range f sw 100 1000 khz bias voltage at rt/sync v rt 1 v maximum duty cycle d max v cs = 0v; MAX16833/MAX16833b only 87.5 88.5 89.5 % v cs = 0v; MAX16833c/MAX16833d only 93 94 95 oscillator frequency accuracy -5 +5 % maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
3 electrical characteristics (continued) (v in = 12v, r rt = 12.4ki, c in = c vcc = 1f, c lframp /c ref = 0.1f, ndrv = comp = dimout = pwmdim = flt = unconnected, v ovp = v cs = v pgnd = v sgnd = 0v, v isense+ = v isense- = 45v, v ictrl = 1.40v, t a = t j = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 2) parameter symbol conditions min typ max units synchronization logic-high input v ih-sync v rt rising 3.8 v synchronization frequency range f syncin 1.1f sw 1.7f sw slope compensation slope compensation current-ramp height i slope ramp peak current added to cs input per switching cycle 46 50 54 fa dithering ramp generator (lframp) (MAX16833/MAX16833c only) charging current v lframp = 0v 80 100 120 fa discharging current v lframp = 2.2v 80 100 120 fa comparator high trip threshold 2 v comparator low trip threshold v rt v reference output (ref) (MAX16833b/MAX16833d only) reference output voltage v ref i ref = 0 to 80 fa 1.604 1.636 1.669 v analog dimming (ictrl) input-bias current ib ictrl v ictrl = 0.62v 0 35 200 na led current-sense amplifier isense+ input-bias current ib isense+ v isense+ = 65v, v isense- = 64.8v 200 400 700 fa isense+ input-bias current with dim low ib isense+off v isense+ = 48v, v isense- = 48v, pwmdim = 0 200 fa isense- input-bias current ib isense- v isense+ = 65v, v isense- = 64.8v 2 5 8 fa voltage gain 6.15 v/v current-sense voltage v sense v ictrl = 1.4v 195 199 203 mv v ictrl = 0.616v 100 v ictrl = 0.2465v 38.4 40 41.4 bandwidth bw av dc - 3db 5 mhz comp transconductance gm comp 2100 3500 4900 fs open-loop dc gain av ota 75 db comp input leakage i lcomp -300 +300 na comp sink current i sink 100 400 700 fa comp source current i source 100 400 700 fa pwm comparator input offset voltage v os-pwm 2 v leading-edge blanking 50 ns propagation delay to ndrv t on(min) includes leading-edge blanking time with 10mv overdrive 55 80 110 ns cs limit comparator current-limit threshold v cs_limit 406 418 430 mv cs limit-comparator propagation delay to ndrv t cs_prop 10mv overdrive (excluding leading-edge blanking time) 30 ns leading-edge blanking 50 ns maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
4 electrical characteristics (continued) (v in = 12v, r rt = 12.4ki, c in = c vcc = 1f, c lframp /c ref = 0.1f, ndrv = comp = dimout = pwmdim = flt = unconnected, v ovp = v cs = v pgnd = v sgnd = 0v, v isense+ = v isense- = 45v, v ictrl = 1.40v, t a = t j = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 2) parameter symbol conditions min typ max units gate driver (ndrv) peak pullup current i ndrvpu v cc = 7v, v ndrv = 0v 3 a peak pulldown current i ndrvpd v cc = 7v, v ndrv = 7v 3 a rise time t r c ndrv = 10nf 30 ns fall time t f c ndrv = 10nf 30 ns r dson pulldown nmos r ndrvon v comp = 0v, i sink = 100ma 0.25 0.6 1.1 i pwm dimming (pwmdim) on threshold v pwmon 1.19 1.225 1.26 v hysteresis v pwmhy 70 mv pullup resistance r pwmpu 1.7 3 4.5 mi pwmdim to led turn-off time pwmdim falling edge to rising edge on dimout, c dimout = 7nf 2 fs pwmdim to led turn-on time pwmdim rising edge to falling edge on dimout, c dimout = 7nf 3 fs pmos gate driver ( dimout) peak pullup current i dimoutpu v pwmdim = 0v, v isense+ - v dimout = 7v 25 50 80 ma peak pulldown current i dimoutpd v isense+ - v dimout = 0v 10 25 45 ma dimout low voltage with respect to v isense+ -8.7 -7.4 -6.3 v overvoltage protection (ovp) threshold v ovpoff v ovp rising 1.19 1.225 1.26 v hysteresis v ovphy 70 mv input leakage i lovp v ovp = 1.235v -300 +300 na short-circuit hiccup mode short-circuit threshold v short-hic (v isense+ - v isense- ) rising 285 298 310 mv hiccup time t hiccup 8192 clock cycles delay in short-circuit hiccup activation 1 fs buck-boost short-circuit detect buck-boost short-circuit threshold v short-bb (v isense+ - v in ) falling, v in = 12v 1.15 1.55 1.9 v delay in flt assertion from buck-boost short-circuit condition t del-bb-shrt counter increments only when v pwmdim > v pwmon 8192 clock cycles delay in flt deassertion after buck-boost short circuit is removed (consecutive clock- cycle count) counter increments only when v pwmdim > v pwmon 8192 clock cycles maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
5 electrical characteristics (continued) (v in = 12v, r rt = 12.4ki, c in = c vcc = 1f, c lframp /c ref = 0.1f, ndrv = comp = dimout = pwmdim = flt = unconnected, v ovp = v cs = v pgnd = v sgnd = 0v, v isense+ = v isense- = 45v, v ictrl = 1.40v, t a = t j = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 2) note 2: all devices are 100% tested at t a = +25nc. limits over temperature are guaranteed by design. typical operating characteristics (v in = +12v, c vin = c vcc = 1ff, c lframp /c ref = 0.1ff, t a = +25nc, unless otherwise noted.) parameter symbol conditions min typ max units open-drain fault ( flt) output voltage low v ol-flt v in = 4.75v, v ovp = 2v, and i sink = 5ma 40 200 mv output leakage current v flt = 5v 1 fa thermal shutdown thermal-shutdown temperature temperature rising +160 nc thermal-shutdown hysteresis 10 nc in rising/falling uvlo threshold vs. temperature MAX16833 toc01 temperature ( c) in rising/falling uvlo threshold (v) 110 85 60 35 10 -15 4.3 4.4 4.5 4.6 4.7 4.8 4.2 -40 125 v in rising v in falling quiescent current vs. temperature MAX16833 toc02 temperature (c) quiescent current (ma) 110 85 60 35 10 -15 1 2 3 4 0 -40 125 v pwmdim = 0v quiescent current vs. v in MAX16833 toc03 v in (v) quiescent current (ma) 10 0.5 1.0 1.5 2.0 2.5 0 1 100 v in ~ 4.6v v pwmdim = 0v v cc vs. i vcc MAX16833 toc04 i vcc (ma) v cc (v) 45 40 35 30 25 20 15 10 5 6.80 6.85 6.90 6.95 7.00 6.75 05 0 v cc vs. temperature MAX16833 toc05 temperature (c) v cc (v) 110 85 60 35 10 -15 6.80 6.85 6.90 6.95 7.00 7.05 7.10 6.75 -40 125 MAX16833 toc06 temperature (c) 110 85 60 35 10 -15 -8.2 -7.7 -7.2 -6.7 -6.2 -8.7 -40 125 dimout (with respect to isense+) vs. temperature dimout (with respect to isense+) (v) maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
6 typical operating characteristics (continued) (v in = +12v, c vin = c vcc = 1ff, c lframp /c ref = 0.1ff, t a = +25nc, unless otherwise noted.) MAX16833 toc07 temperature (c) dimout rise time (s) 110 85 -15 10 35 60 1.2 1.4 1.6 1.8 2.0 2.2 2.4 1.0 -40 125 dimout rise time vs. temperature c dimout = 6.8nf MAX16833 toc08 temperature (c) 110 85 60 35 10 -15 2.0 2.5 3.0 3.5 4.0 1.5 -40 125 dimout fall time vs. temperature dimout fall time (s) c dimout = 6.8nf v sense vs. temperature MAX16833 toc09 temperature (c) v sense (mv) 110 85 35 60 10 -15 196 197 198 199 200 201 202 203 204 205 195 -40 125 v sense vs. v ictrl MAX16833 toc10 v ictrl (v) v sense (mv) 1.20 1.00 0.60 0.80 0.40 0.20 20 40 60 80 100 120 140 160 180 200 220 240 0 0 1.40 oscillator frequency vs. 1/r rt conductance (MAX16833/MAX16833b only) MAX16833 toc12 1/r rt (k i -1 ) oscillator frequency (khz) 0.121 0.092 0.063 0.034 100 200 300 400 500 600 700 800 900 1000 1100 0 0.005 0.150 oscillator frequency vs. temperature (MAX16833/MAX16833b only) MAX16833 toc11 temperature (c) oscillator frequency (khz) 110 85 35 60 10 -15 292 294 296 298 300 302 304 306 308 310 290 -40 125 r rt = 24.9k i maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
7 typical operating characteristics (continued) (v in = +12v, c vin = c vcc = 1ff, c lframp /c ref = 0.1ff, t a = +25nc, unless otherwise noted.) pin configuration ndrv rise/fall time vs. temperature MAX16833 toc13 temperature (c) ndrv rise/fall time (ns) 110 85 60 35 10 -15 30 40 50 60 20 -40 125 ndrv rise time c ndrv = 10nf ndrv fall time 600hz dimming operation MAX16833 toc14 i led 500ma/div 0v 0v 0v 0v 0ma 0v v comp 2v/div v ndrv 10v/div 400s/div v dimout 50v/div pwmdim = 600hz 16 15 14 13 12 11 10 1 2 3 4 5 6 7 in v cc ndrv pgnd ictrl sgnd rt/sync lframp (ref) top view MAX16833 MAX16833b MAX16833c MAX16833d cs isense+ isense- pwmdim 9 8ovp *ep *ep = exposed pad. ( ) for MAX16833b/MAX16833d only. comp tssop + flt dimout maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
8 pin description pin name function 1 lframp (MAX16833/ MAX16833c) low-frequency ramp output. connect a capacitor from lframp to ground to program the ramp frequency, or connect to sgnd if not used. a resistor can be connected between lframp and rt/ sync to dither the pwm switching frequency to achieve spread spectrum. ref (MAX16833b/ MAX16833d) 1.64v reference output. connect a 1ff ceramic capacitor from ref to sgnd to provide a stable reference voltage. connect a resistive divider from ref to ictrl for analog dimming. 2 rt/sync pwm switching frequency programming input. connect a resistor (r rt ) from rt/sync to sgnd to set the internal clock frequency. frequency = (7.350 x 10 9 )/r rt for the MAX16833/MAX16833b. frequency = (6.929 x10 9 )/r rt for the MAX16833c/MAX16833d. an external pulse can be applied to rt/sync through a coupling capacitor to synchronize the internal clock to the external pulse frequency. the parasitic capacitance on rt/sync should be minimized. 3 sgnd signal ground 4 ictrl analog dimming-control input. the voltage at ictrl sets the led current level when v ictrl < 1.2v. for v ictrl > 1.4v, the internal reference sets the led current. 5 comp compensation network connection. for proper compensation, connect a suitable rc network from comp to ground. 6 flt active-low, open-drain fault indicator output. see the fault indicator (flt) section. 7 pwmdim pwm dimming input. when pwmdim is pulled low, dimout is pulled high and pwm switching is disabled. pwmdim has an internal pullup resistor, defaulting to a high state when left unconnected. 8 ovp led string overvoltage-protection input. connect a resistive divider between isense+, ovp, and sgnd. when the voltage on ovp exceeds 1.23v, a fast-acting comparator immediately stops pwm switching. this comparator has a hysteresis of 70mv. 9 dimout active-low external dimming p-channel mosfet gate driver 10 isense- negative led current-sense input. a 100i resistor is recommended to be connected between isense- and the negative terminal of the led current-sense resistor. this preserves the absolute maximum rating of the isense- pin during led short circuit. 11 isense+ positive led current-sense input. the voltage between isense+ and isense- is proportionally regulated to the lesser of v ictrl or 1.23v. 12 cs switching regulator current-sense input. add a resistor from cs to switching mosfet current-sense resistor terminal for programming slope compensation. 13 pgnd power ground 14 ndrv external n-channel mosfet gate-driver output 15 v cc 7v low-dropout voltage regulator output. bypass v cc to pgnd with a 1ff (min) ceramic capacitor. 16 in positive power-supply input. bypass in to pgnd with at least a 1ff ceramic capacitor. ep exposed pad. connect ep to the ground plane for heatsinking. do not use ep as the only electrical connection to ground. maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
9 MAX16833/MAX16833c functional diagram MAX16833 MAX16833c in cs lframp ictrl isense+ isense- pwmdim ovp rt/ sync v cc v cc ndrv pgnd reset dominant pwm comp max duty cycle s r q s r q uvlo uvlo rt oscillator slope compensation ramp generation cs/pwm blanking 0.42v 6.15 6.15 x 0.3v 1s delay 8192 x t osc hiccup timer v isense+ - 7v isense+ sync buck-boost short detection tshdn sgnd flt dimout comp v bg 3.3v v bg 3mi gm v bg lpf min out 2v thermal shutdown lvsh tshdn 5.7v 5v 5v v bg 5v reg bg 7v ldo 200ki maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
10 MAX16833b/MAX16833d functional diagram MAX16833b MAX16833d in cs ref ictrl isense+ isense- pwmdim ovp rt/ sync v cc v cc ndrv pgnd reset dominant pwm comp max duty cycle s r q s r q uvlo uvlo rt oscillator slope compensation 1.64v (80a) reference cs/pwm blanking 0.42v 6.15 6.15 x 0.3v 1s delay 8192 x t osc hiccup timer v isense+ - 7v isense+ sync buck-boost short detection tshdn sgnd flt dimout comp v bg 3.3v vbg 3mi gm v bg lpf min out 2v thermal shutdown lvsh tshdn 5.7v 5v 5v v bg 5v reg bg 7v ldo 200ki maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
11 detailed description the MAX16833/MAX16833bCMAX16833d are peak current-mode-controlled led drivers for boost, buck- boost, sepic, flyback, and high-side buck topologies. a low-side gate driver capable of sinking and sourcing 3a can drive a power mosfet in the 100khz to 1mhz fre - quency range. constant-frequency peak current-mode control is used to control the duty cycle of the pwm controller that drives the power mosfet. externally pro - grammable slope compensation prevents subharmonic oscillations for duty cycles exceeding 50% when the inductor is operating in continuous conduction mode. most of the power for the internal control circuitry inside the ics is provided from an internal 5v regulator. the gate drive for the low-side switching mosfet is pro - vided by a separate v cc regulator. a dimming driver designed to drive an external p-channel in series with the led string provides wide-range dimming control. this dimming driver is powered by a separate unconnected reference -7v regulator. this feature provides extremely fast pwm current switching to the leds with no transient overvoltage or undervoltage conditions. in addition to pwm dimming, the ics provide analog dimming using a dc input at the ictrl input. a single resistor from rt/sync to ground sets the switching frequency from 100khz to 1mhz, while an external clock signal capacitively coupled to rt/sync allows the ics to synchronize to an external clock. the switching frequency can be dithered for spread-spectrum applications by connecting the lframp output to rt/sync through an external resistor in the MAX16833/MAX16833c. in the MAX16833b/MAX16833d, the lframp output is replaced by a ref output, which provides a regulated 1.64v, 2% accurate reference that can be used with a resistive divider from ref to ictrl to set the led cur- rent. the maximum current from the ref output cannot exceed 80fa. additional features include a fault-indicator output ( flt) for short, overvoltage, or overtemperature conditions and an overvoltage-protection (ovp) sense input for overvoltage protection. in case of led string short, for a buck-boost configuration, the short-circuit current is equal to the programmed led current. in the case of boost configuration, the ics enter hiccup mode with automatic recovery from short circuit. uvlo the ics feature undervoltage lockout (uvlo) using the positive power-supply input (in). the ics are enabled when v in exceeds the 4.6v (typ) threshold and are dis - abled when v in drops below the 4.35v (typ) threshold. the uvlo is internally fixed and cannot be adjusted. there is a startup delay of 300s (typ) + 64 switching clock cycles on power-up after the uvlo threshold is crossed. there is a 3.3fs delay on power-down on the falling edge of the uvlo. dimming mosfet driver (dimout) the ics require an external p-channel mosfet for pwm dimming. for normal operation, connect the gate of the mosfet to the output of the dimming driver ( dimout). the dimming driver can sink up to 25ma or source up to 50ma of peak current for fast charging and discharg - ing of the p-mosfet gate. when the pwmdim signal is high, this driver pulls the p-mosfet gate to 7v below the isense+ pin to completely turn on the p-channel dimming mosfet. n-channel mosfet switch driver (ndrv) the ics drive an external n-channel switching mosfet. ndrv swings between v cc and pgnd. ndrv can sink/ source 3a of peak current, allowing the ics to switch mosfets in high-power applications. the average cur - rent demanded from the supply to drive the external mosfet depends on the total gate charge (q g ) and the operating frequency of the converter, f sw . use the following equation to calculate the driver supply current i ndrv required for the switching mosfet: i ndrv = q g x f sw pulse-dimming input (pwmdim) the ics offer a dimming input (pwmdim) for pulse-width modulating the output current. pwm dimming can be achieved by driving pwmdim with a pulsating voltage source. when the voltage at pwmdim is greater than 1.23v, the pwm dimming p-channel mosfet turns on and the gate drive to the n-channel switching mosfet is also enabled. when the voltage on pwmdim drops 70mv below 1.23v, the pwm dimming mosfet turns off and the n-channel switching mosfet is also turned off. the comp capacitor is also disconnected from the internal transconductance amplifier when pwmdim is low. when left unconnected, a weak internal pullup resistor sets this input to logic-high. maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
12 analog dimming (ictrl) the ics offer an analog dimming control input (ictrl). the voltage at ictrl sets the led current level when v ictrl < 1.2v. the led current can be linearly adjusted from zero with the voltage on ictrl. for v ictrl > 1.4v, an internal reference sets the led current. the maximum withstand voltage of this input is 5.5v. low-side linear regulator (v cc ) the ics feature a 7v low-side linear regulator (v cc ). v cc powers up the switching mosfet driver with sourc - ing capability of up to 50ma. use a 1 ff (min) low-esr ceramic capacitor from v cc to pgnd for stable opera - tion. the v cc regulator goes below 7v if the input volt - age falls below 7v. the dropout voltage for this regulator at 50ma is 0.2v. this means that for an input voltage of 5v, the v cc voltage is 4.8v. the short-circuit current on the v cc regulator is 100ma (typ). connect v cc to in if v in is always less than 7v. led current-sense inputs (isense) the differential voltage from isense+ to isense- is fed to an internal current-sense amplifier. this amplified sig - nal is then connected to the negative input of the trans - conductance error amplifier. the voltage-gain factor of this amplifier is 6.15. the offset voltage for this amplifier is p 1mv. internal transconductance error amplifier the ics have a built-in transconductance amplifier used to amplify the error signal inside the feedback loop. when the dimming signal is low, comp is disconnected from the output of the error amplifier and dimout goes high. when the dimming signal is high, the output of the error amplifier is connected to comp and dimout goes low. this enables the compensation capacitor to hold the charge when the dimming signal has turned off the internal switching mosfet gate drive. to maintain the charge on the compensation capacitor c comp (c4 in the typical operating circuits), the capacitor should be a low-leakage ceramic type. when the internal dim - ming signal is enabled, the voltage on the compensation capacitor forces the converter into steady state almost instantaneously. internal oscillator (rt/sync) the internal oscillators of the ics are programmable from 100khz to 1mhz using a single resistor at rt/sync. use the following formula to calculate the switching fre - quency: ( ) ( ) osc rt osc rt 7350 k f (khz) for the MAX16833 MAX16833b r (k ) 6929 k f (khz) for the MAX16833c MAX16833d r (k ) ? = ? ? = ? where r rt is the resistor from rt/sync to sgnd. synchronize the oscillator with an external clock by ac-coupling the external clock to the rt/sync input. for f osc between 200khz and 1mhz, the capacitor used for the ac-coupling should satisfy the following relation: -6 -9 sync rt 9.8624 10 c 0.144 10 farads r ? where r rt is in k. for f osc below 200ghz, c sync 268nf. the pulse width for the synchronization pulse should satisfy the following relations: clk pw pw clk s clk osc 1.05 t tt 0.5 and 1- tv t t ?? << ?? ?? pw ss clk t 3.4v 0.8 - v v 5v t ?? < +< ?? ?? where t pw is the synchronization source pulse width, t clk is the synchronization clock time period, t osc is the free-running oscillator time period, and v s is the syn - chronization pulse-voltage level. ensure that the external clock signal frequency is at least 1.1 x f osc, where f osc is the oscillator frequency set by r rt . a typical pulse width of 200ns can be used for proper synchronization of a frequency up to 250khz. a rising external clock edge (sync) is interpreted as a syn - chronization input. if the sync signal is lost, the internal oscillator takes control of the switching rate returning the switching frequency to that set by r rt . this maintains output regulation even with intermittent sync signals. maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
13 figure 1 shows the frequency-synchronization circuit suitable for applications where a 5v amplitude pulse with 20% to 80% duty cycle is available as the synchronization source. this circuit can be used for sync frequencies in the 100khz to 1mhz range. c1 and r2 act as a dif - ferentiator that reduces the input pulse width to suit the ics rt/sync input. d2 bypasses the negative current through c1 at the falling edge of the sync source to limit the minimum voltage at the rt/sync pin. the differentia - tor output is ac-coupled to the rt/sync pin through c2. the output impedance of the sync source should be low enough to drive the current through r2 on the rising edge. the rise/fall times of the sync source should be less than 50ns to avoid excessive voltage drop across c1 during the rise time. the amplitude of the sync source can be between 4v and 5v. if the sync source amplitude is 5v and the rise time is less than 20ns, then the maxi- mum peak voltage at rt/sync pin can get close to 6v. under such conditions, it is desirable to use a resistor in series with c1 to reduce the maximum voltage at the rt/ sync pin. for proper synchronization, the peak sync pulse voltage at rt/sync pin should exceed 3.8v. frequency dithering (lframp/MAX16833/ MAX16833c) the MAX16833/MAX16833c feature a low-frequency ramp output. connect a capacitor from lframp to ground to program the ramp frequency. connect to sgnd if not used. a resistor can be connected between lframp and rt/sync to dither the pwm switching frequency to achieve spread spectrum. a lower value resistor provides a larger amount of frequency dithering. the lframp voltage is a triangular waveform between 1v (typ) and 2v (typ). the ramp frequency is given by: lframp lframp 50 a f (hz) c (f) = f voltage-reference output (ref/MAX16833b/MAX16833d) the MAX16833b/MAX16833d have a 2% accurate 1.64v reference voltage on the ref output. connect a 1 ff ceramic capacitor from ref to sgnd to provide a stable reference voltage. this reference can supply up to 80a. this output can drive a resistive divider to the ictrl input for analog dimming. the resistance from ref to ground should be greater than 20.5k i. switching mosfet current-sense input (cs) cs is part of the current-mode control loop. the switch - ing control uses the voltage on cs, set by r cs (r4 in the typical operating circuits ) and r slope (r1 in the typical operating circuits ), to terminate the on pulse width of the switching cycle, thus achieving peak current-mode con- trol. internal leading-edge blanking of 50ns is provided to prevent premature turn-off of the switching mosfet in each switching cycle. resistor r cs is connected between the source of the n-channel switching mosfet and pgnd. during switching, a current ramp with a slope of 50 f a x f sw is sourced from the cs input. this current ramp, along with resistor r slope , programs the amount of slope compensation. overvoltage-protection input (ovp) ovp sets the overvoltage-threshold limit across the leds. use a resistive divider between isense+ to ovp and sgnd to set the overvoltage-threshold limit. an internal overvoltage-protection comparator senses the differential voltage across ovp and sgnd. if the dif - ferential voltage is greater than 1.23v, ndrv goes low, dimout goes high, and flt asserts. when the differen - tial voltage drops by 70mv, ndrv is enabled, dimout goes low, and flt deasserts. fault indicator (flt) the ics feature an active-low, open-drain fault indicator (flt). flt goes low when one of the following conditions occur: u overvoltage across the led string u short-circuit condition across the led string u overtemperature condition flt goes high when the fault condition ends. figure 1. sync circuit r2 22i d2 sd103aws r rt 24.9i c2 1000pf rt pin gnd gnd c1 680pf sync maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
14 thermal protection the ics feature thermal protection. when the junction temperature exceeds +160 n c, the ics turn off the external power mosfets by pulling the ndrv low and dimout high. external mosfets are enabled again after the junc - tion temperature has cooled by 10c. this results in a cycled output during continuous thermal-overload condi- tions. thermal protection protects the ics in the event of fault conditions. short-circuit protection boost configuration in the boost configuration, if the led string is shorted it causes the (isense+ to isense-) voltage to exceed 300mv. if this condition occurs for r 1 f s, the ics activates the hiccup timer for 8192 clock cycles during which: u ndrv goes low and dimout goes high. u the error amplifier is disconnected from comp. u flt is pulled to sgnd. after the hiccup time has elapsed, the ics retry. during this retry period, flt is latched and is reset only if there is no short detected after 20 f s of retrying. buck-boost configuration in the case of the buck-boost configuration, once an led string short occurs the behavior is different. the ics maintain the programmed current across the short. in this case, the short is detected when the voltage between isense+ and in falls below 1.5v. a buck-boost short fault starts an up counter and flt is asserted only after the counter has reached 8192 clock cycles con- secutively. if for any reason (v isense+ - v in > 1.5v), the counter starts down counting, resulting in flt being deasserted only after 8192 consecutive clock cycles of (v isense+ - v in > 1.5v) condition. exposed pad the ics package features an exposed thermal pad on its underside that should be used as a heatsink. this pad lowers the packages thermal resistance by provid- ing a direct heat-conduction path from the die to the pcb. connect the exposed pad and gnd to the system ground using a large pad or ground plane, or multiple vias to the ground plane layer. applications information setting the overvoltage threshold the overvoltage threshold is set by resistors r5 and r11 (see the typical operating circuits ). the overvoltage circuit in the ics is activated when the voltage on ovp with respect to gnd exceeds 1.23v. use the following equation to set the desired overvoltage threshold: v ov = 1.23v (r5 + r11)/r11 programming the led current normal sensing of the led current should be done on the high side where the led current-sense resistor is connected to the boost output. the other side of the led current-sense resistor goes to the source of the p-channel dimming mosfet if pwm dimming is desired. the led current is programmed using r7. when v ictrl > 1.23v, the internal reference regulates the voltage across r7 to 200mv: led 200mv i r7 = the led current can also be programmed using the voltage on ictrl when v ictrl < 1.2v (analog dimming). the voltage on ictrl can be set using a resistive divider from the ref output in the case of the MAX16833b/ MAX16833d. the current is given by: ictrl led v i r7 6.15 = where: ( ) ref ictrl v r8 v r8 r9 = + where v ref is 1.64v and resistors r8 and r9 are in ohms. at higher led currents there can be noticeable ripple on the voltage across r7. high-ripple voltages can cause a noticeable difference between the programmed value of the led current and the measured value of the led current. to minimize this error, the ripple voltage across r7 should be less than 40mv. maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
15 inductor selection boost configuration in the boost converter (see the typical operating circuits), the average inductor current varies with the line voltage. the maximum average current occurs at the lowest line voltage. for the boost converter, the average inductor current is equal to the input current. calculate maximum duty cycle using the following equation: led d inmin max led d fet v v - v d v v -v + = + where v led is the forward voltage of the led string in volts, v d is the forward drop of rectifier diode d1 in volts (approximately 0.6v), v inmin is the minimum input- supply voltage in volts, and v fet is the average drain-to- source voltage of the mosfet q1 in volts when it is on. use an approximate value of 0.2v initially to calculate d max . a more accurate value of the maximum duty cycle can be calculated once the power mosfet is selected based on the maximum inductor current. use the following equations to calculate the maximum average inductor current il avg , peak-to-peak induc - tor current ripple di l , and peak inductor current il p in amperes: led avg max i il 1- d = allowing the peak-to-peak inductor ripple to be di l, the peak inductor current is given by: l p avg i il il 2 ? = + the inductance value (l) of inductor l1 in henries (h) is calculated as: ( ) inmin fet max sw l v -v d l fi = ? where f sw is the switching frequency in hertz, v inmin and v fet are in volts, and di l is in amperes. choose an inductor that has a minimum inductance greater than the calculated value. the current rating of the inductor should be higher than il p at the operating temperature. buck-boost configuration in the buck-boost led driver (see the typical operating circuits), the average inductor current is equal to the input current plus the led current. calculate the maxi - mum duty cycle using the following equation: led d max led d inmin fet v v d v v v -v + = ++ where v led is the forward voltage of the led string in volts, v d is the forward drop of rectifier diode d1 (approximately 0.6v) in volts, v inmin is the minimum input supply voltage in volts, and v fet is the average drain-to-source voltage of the mosfet q1 in volts when it is on. use an approximate value of 0.2v initially to cal - culate d max . a more accurate value of maximum duty cycle can be calculated once the power mosfet is selected based on the maximum inductor current. use the equations below to calculate the maximum aver - age inductor current il avg , peak-to-peak inductor cur - rent ripple di l , and peak inductor current il p in amperes: led avg max i il 1- d = allowing the peak-to-peak inductor ripple to be di l: l p avg i il il 2 ? = + where il p is the peak inductor current. the inductance value (l) of inductor l1 in henries is calculated as: ( ) inmin fet max sw l v -v d l fi = ? where f sw is the switching frequency in hertz, v inmin and v fet are in volts, and di l is in amperes. choose an inductor that has a minimum inductance greater than the calculated value. peak current-sense resistor (r4) the value of the switch current-sense resistor r4 for the boost and buck-boost configurations is calculated as follows: sc p 0.418v - v r4 il = ? where il p is the peak inductor current in amperes and v sc is the peak slope compensation voltage. maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
16 slope compensation slope compensation should be added to converters with peak current-mode control operating in continuous- conduction mode with more than 50% duty cycle to avoid current-loop instability and subharmonic oscilla- tions. the minimum amount of slope compensation that is required for stability is: v scmin = 0.5 (inductor current downslope - inductor current upslope) x r4 in the ics, the slope-compensating ramp is added to the current-sense signal before it is fed to the pwm com - parator. connect a resistor (r1) from cs to the inductor current-sense resistor terminal to program the amount of slope compensation. the ics generate a current ramp with a slope of 50 fa/ t osc for slope compensation. the current-ramp signal is forced into the external resistor (r1) connected between cs and the source of the external mosfet, thereby adding a programmable slope compensating voltage (v scomp ) at the current-sense input cs. therefore: dv sc /dt = (r1 x 50 fa)/t osc in v/s the minimum value of the slope-compensation voltage that needs to be added to the current-sense signal at peak current and at minimum line voltage is: max led inmin min min sw (d (v - 2v ) r4) sc (v) boost 2l f = max led inmin min min sw (d (v - v ) r4) sc (v)buck-boost 2l f = where f sw is the switching frequency, d max is the maxi- mum duty cycle, which occurs at low line, v inmin is the minimum input voltage, and l min is the minimum value of the selected inductor. for adequate margin, the slope-com- pensation voltage is multiplied by a factor of 1.5. therefore, the actual slope-compensation voltage is given by: v sc = 1.5sc min from the previous formulas, it is possible to calculate the value of r4 as: for boost configuration: led inmin p max min sw 0.418v r4 v 2v il 0.75d lf ? = + for buck-boost configuration: led inmin p max min sw 0.418v r4 vv il 0.75d lf ? = + the minimum value of the slope-compensation resistor (r1) that should be used to ensure stable operation at minimum input supply voltage can be calculated as: for boost configuration: led inmin min sw (v 2v ) r4 1.5 r1 2 l f 50 a ? = for buck-boost configuration : led inmin min sw (v v ) r4 1.5 r1 2 l f 50 a ? = where f sw is the switching frequency in hertz, v inmin is the minimum input voltage in volts, v led is the led voltage in volts, d max is the maximum duty cycle, il p is the peak inductor current in amperes, and l min is the minimum value of the selected inductor in henries. output capacitor the function of the output capacitor is to reduce the output ripple to acceptable levels. the esr, esl, and the bulk capacitance of the output capacitor contribute to the output ripple. in most applications, the output esr and esl effects can be dramatically reduced by using low-esr ceramic capacitors. to reduce the esl and esr effects, connect multiple ceramic capacitors in par - allel to achieve the required bulk capacitance. to mini- mize audible noise generated by the ceramic capacitors during pwm dimming, it could be necessary to minimize the number of ceramic capacitors on the output. in these cases, an additional electrolytic or tantalum capacitor provides most of the bulk capacitance. boost and buck-boost configurations the calculation of the output capacitance is the same for both boost and buck-boost configurations. the output rip - ple is caused by the esr and the bulk capacitance of the output capacitor if the esl effect is considered negligible. for simplicity, assume that the contributions from esr and the bulk capacitance are equal, allowing 50% of the ripple for the bulk capacitance. the capacitance is given by: led max out outripple sw i 2d c vf maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
17 where i led is in amperes, c out is in farads, f sw is in hertz, and v outripple is in volts. the remaining 50% of allowable ripple is for the esr of the output capacitor. based on this, the esr of the output capacitor is given by: outripple cout p v esr ( ) (il 2) MAX16833/MAX16833bCMAX16833d
18 boost configuration 2 av g led gd sw sw on off il v c f p 2 11 ig ig ?? ?? = ?? ?? ?? + ?? ?? buck-boost configuration 2 av g led inmax gd sw sw on off il (v v ) c f p 2 11 ig ig ?? + ?? = ?? ?? ?? + ?? ?? where ig on and ig off are the gate currents of the mosfet q1 in amperes when it is turned on and turned off, respectively, v led and v inmax are in volts, il avg is in amperes, f sw is in hertz, and c gd is the gate-to-drain mosfet capacitance in farads. rectifier diode use a schottky diode as the rectifier (d1) for fast switch - ing and to reduce power dissipation. the selected schottky diode must have a voltage rating 20% above the maximum converter output voltage. the maximum converter output voltage is v led in boost configuration and v led + v inmax in buck-boost configuration. the current rating of the diode should be greater than i d in the following equation: i d = il avg x (1 - d max ) x 1.5 dimming mosfet select a dimming mosfet (q2) with continuous current rating at the operating temperature higher than the led current by 30%. the drain-to-source voltage rating of the dimming mosfet must be higher than v led by 20%. feedback compensation the led current control loop comprising the switching converter, the led current amplifier, and the error ampli - fier should be compensated for stable control of the led current. the switching converter small-signal transfer function has a right-half-plane (rhp) zero for both boost and buck-boost configurations as the inductor current is in continuous conduction mode. the rhp zero adds a 20db/decade gain together with a 90-degree phase lag, which is difficult to compensate. the easiest way to avoid this zero is to roll off the loop gain to 0db at a frequency less than 1/5 the rhp zero frequency with a -20db/decade slope. the worst-case rhp zero frequency (f zrhp ) is calcu- lated as follows: boost configuration 2 led max zrhp led v (1- d ) f 2 li = buck-boost configuration 2 led max zrhp led max v (1- d ) f 2 li d = where f zrhp is in hertz, v led is in volts, l is the induc - tance value of l1 in henries, and i led is in amperes. the switching converter small-signal transfer function also has an output pole for both boost and buck-boost configurations. the effective output impedance that determines the output pole frequency together with the output filter capacitance is calculated as follows: boost configuration led led out led led led (r r7) v r (r r7) i v + = + + buck-boost configuration led led out led led max led (r r7) v r (r r7) i d v + = + + where r led is the dynamic impedance of the led string at the operating current in ohms, r7 is the led current - sense resistor in ohms, v led is in volts, and i led is in amperes. the output pole frequency for both boost and buck- boost configurations is calculated as below: p2 out out 1 f 2c r = where f p2 is in hertz, c out is the output filter capaci - tance in farads, and r out is the effective output imped - ance in ohms calculated above. the feedback loop compensation is done by connecting resistor r10 and capacitor c4 in series from the comp pin to gnd. r10 is chosen to set the high-frequency gain of the integrator to set the crossover frequency at f zrhp /5 and c4 is chosen to set the integrator zero frequency to maintain loop stability. for optimum performance, choose the components using the following equations: zrhp c max comp 2 f r4 r1 0 f (1 d ) r7 6.15 gm ? = maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
19 the value of c4 can be calculated as below: zrhp 25 c4 r1 0 f = where r10 is the compensation resistor in ohms, f zrhp and f p2 are in hertz, r4 is the inductor current-sense resistor in ohms, r7 is the led current-sense resistor in ohms, factor 6.15 is the gain of the led current-sense amplifier, and gm comp is the transconductance of the error amplifier in amps/volts. layout recommendations typically, there are two sources of noise emission in a switching power supply: high di/dt loops and high dv/dt surfaces. for example, traces that carry the drain cur - rent often form high di/dt loops. similarly, the heatsink of the mosfet connected to the device drain presents a dv/dt source; therefore, minimize the surface area of the heatsink as much as is compatible with the mosfet power dissipation or shield it. keep all pcb traces car - rying switching currents as short as possible to minimize current loops. use ground planes for best results. careful pcb layout is critical to achieve low switching losses and clean, stable operation. use a multilayer board whenever possible for better noise immunity and power dissipation. follow these guidelines for good pcb layout: u use a large contiguous copper plane under the ics package. ensure that all heat-dissipating compo - nents have adequate cooling. u isolate the power components and high-current paths from the sensitive analog circuitry. u keep the high-current paths short, especially at the ground terminals. this practice is essential for stable, jitter-free operation. keep switching loops short such that: a) the anode of d1 must be connected very close to the drain of the mosfet q1. b) the cathode of d1 must be connected very close to c out . c) c out and current-sense resistor r4 must be con - nected directly to the ground plane. u connect pgnd and sgnd at a single point. u keep the power traces and load connections short. this practice is essential for high efficiency. use thick copper pcbs (2oz vs. 1oz) to enhance full-load efficiency. u route high-speed switching nodes away from the sensitive analog areas. use an internal pcb layer for the pgnd and sgnd plane as an emi shield to keep radiated noise away from the device, feedback dividers, and analog bypass capacitors. maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
20 typical operating circuits pwmdim boost headlamp driver r3 r1 r2 r4 r10 r5 c3 r9 r8 c1 in ndrv cs ovp isense+ isense- flt comp c4 c2 lframp rt/sync v cc ictrl sgnd pgnd ep v in 6v to 18v with load dump up to 70v r11 led+ led- pwmdim q1 d1 l1 q2 dimout r7 MAX16833 MAX16833c pwmdim buck-boost headlamp driver r3 r1 r2 r4 r10 r5 c3 r9 r8 c1 in ndrv cs ovp isense+ isense- flt comp c4 c2 ref rt/sync v cc ictrl sgnd pgnd ep v in 6v to 18v with load dump up to 70v r11 led+ led- pwmdim q1 d1 l1 q2 dimout r7 MAX16833b MAX16833d maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
21 ordering information (continued) chip information process: bicmos-dmos package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. /v denotes an automotive qualified part. package type package code outline no. land pattern no. 16 tssop-ep u16e+3 21-0108 90-0120 part temp range pin-package functionality max duty cycle (%) MAX16833baue+ -40c to +125c 16 tssop-ep* reference voltage output 88.5 MAX16833baue/v+ -40c to +125c 16 tssop-ep* reference voltage output 88.5 MAX16833caue+ -40c to +125c 16 tssop-ep* frequency dithering 94 MAX16833caue/v+ -40c to +125c 16 tssop-ep* frequency dithering 94 MAX16833daue+ -40c to +125c 16 tssop-ep* reference voltage output 94 MAX16833daue/v+ -40c to +125c 16 tssop-ep* reference voltage output 94 maxim integrated high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 22 maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ? 2013 maxim integrated maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 6/10 initial release 1 11/10 added MAX16833aue 1, 21, 22 2 12/10 added MAX16833c and MAX16833d 22 3 7/11 added MAX16833e 1C4, 6C14, 20, 21 4 8/12 removed MAX16833e 1C22 5 4/13 updated startup delay time and its description 2, 11 6 8/13 updated functional diagrams and the MAX16833b/MAX16833d typical operating circuit 9, 10, 20 high-voltage hb led drivers with integrated high-side current sense MAX16833/MAX16833bCMAX16833d

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